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PPC405EP-3GB200C 参数 Datasheet PDF下载

PPC405EP-3GB200C图片预览
型号: PPC405EP-3GB200C
PDF下载: 下载PDF文件 查看货源
内容描述: 405EP的PowerPC嵌入式处理器 [PowerPC 405EP Embedded Processor]
分类和应用: PC
文件页数/大小: 50 页 / 805 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – September 10, 2007  
PPC405EP – PowerPC 405EP Embedded Processor  
Address Maps  
Data Sheet  
The PPC405EP incorporates two address maps. The first address map defines the possible use of addressable  
memory regions that the processor can access. The second address map defines Device Configuration Register  
(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EP processor through  
the use of mtdcr and mfdcr instructions.  
Table 1. System Memory Address Map (4GB System Memory)  
Function  
Subfunction  
Start Address  
0x00000000  
0xE8010000  
0xEC000000  
0xEEE00000  
0xEF500000  
0xEF900000  
0xFFE00000  
End Address  
0xE7FFFFFF  
0xE87FFFFF  
0xEEBFFFFF  
0xEF3FFFFF  
0xEF5FFFFF  
0xFFFFFFFF  
0xFFFFFFFF  
Size  
3712MB  
8MB  
SDRAM, External Peripherals, and PCI  
Memory  
44MB  
6MB  
General Use  
Note: Any of the address ranges listed at  
right may be use for any of the above  
functions.  
1MB  
263MB  
2MB  
Peripheral Bus Boot 1  
Boot-up  
PCI  
PCI Boot 2  
0xFFFE0000  
0xE8000000  
0xE8800000  
0xEEC00000  
0xEED00000  
0xEF400000  
0xEF600000  
0xEF600300  
0xEF600400  
0xEF600500  
0xEF600600  
0xEF600700  
0xEF600800  
0xEF600900  
0xFFFFFFFF  
0xE800FFFF  
0xEBFFFFFF  
0xEEC00007  
0xEED00003  
0xEF40003F  
0xEF6000FF  
0xEF600307  
0xEF600407  
0xEF60051F  
0xEF60063F  
0xEF60077F  
0xEF6008FF  
0xEF6009FF  
128KB  
64KB  
56MB  
8B  
PCI I/O  
PCI I/O  
Configuration Registers  
Interrupt Acknowledge and Special Cycle  
Local Configuration Registers  
GPT  
4B  
64B  
256B  
8B  
UART0  
UART1  
8B  
IIC0  
32B  
Internal Peripherals  
OPB Arbiter  
64B  
GPIO Controller Registers  
Ethernet 0 Controller Registers  
Ethernet 1 Controller Registers  
128B  
256B  
256B  
Notes:  
1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.  
2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.  
3. After the boot process, software may reassign the boot memory regions for other uses.  
4. All address ranges not listed above are reserved.  
6
AMCC