Part Number PPC405EP
Revision 1.07 – September 10, 2007
Data Sheet
PPC405EP
PowerPC 405EP Embedded Processor
Features
®
- Asynchronous PCI Bus interface
- Internal or external PCI Bus Arbiter
•
•
AMCC PowerPC 405 32-bit RISC processor
core operating up to 333MHz with 16KB D-
and I-caches
•
•
Two Ethernet 10/100Mbps (full-duplex) ports
with media independent interface (MII)
PC-133 synchronous DRAM (SDRAM) inter-
face
Programmable interrupt controller supports
seven external and 19 internal edge-triggered
or level-sensitive interrupts
- 32-bit interface for non-ECC applications
4KB on-chip memory (OCM)
•
•
•
•
•
•
•
•
•
Programmable timers
External peripheral bus
Software accessible event counters
Two serial ports (16750 compatible UART)
One IIC interface
- Flash ROM/Boot ROM interface
- Direct support for 8- or 16-bit SRAM and
external peripherals
General purpose I/O (GPIO) available
Supports JTAG for board level testing
- Up to five devices
•
•
DMA support for memory and UARTs.
- Scatter-gather chaining supported
- Four channels
Internal processor local bus (PLB) runs at
SDRAM interface frequency
•
Supports PowerPC processor boot from PCI
memory
PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
Description
Designed specifically to address embedded
applications, the PowerPC 405EP (PPC405EP)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
Ethernet interface, control for external ROM and
peripherals, DMA with scatter-gather support, serial
ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-27E, 0.18 μm (0.11 μm L )
eff
Package: 31mm, 385-ball, enhanced plastic ball grid
array (E-PBGA)
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus interface,
Power (typical): 0.72W at 266MHz
AMCC
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
