Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing value of na means “not applicable” and dc means
“don’t care.”
2. See “Test Conditions” on page 31 for output capacitive loading.
3. I/O H is specified at 2.4V; I/O L is specified at 0.4V
Table 13. I/O Specifications—All speeds
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
(TIS min)
(TIH min)
Internal Peripheral Interface
IICSCL
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
19
19
12
12
12
12
12
12
12
12
12
12
8
IICSDA
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
8
8
8
n/a
n/a
n/a
n/a
8
UART0_RTS
UART0_Rx
n/a
n/a
8
8
UART0_Tx
n/a
n/a
n/a
n/a
8
UART1_RTS
[UART1_DTR]
12
8
UART1_DSR
[UART1_CTS]
n/a
n/a
n/a
n/a
n/a
n/a
UART1_Rx
UART1_Tx
UARTSerClk
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK
n/a
12
n/a
8
n/a
n/a
n/a
n/a
n/a
n/a
12
8
n/a
n/a
12
n/a
n/a
8
async
async
async
async
async
TDI
TDO
TMS
n/a
n/a
n/a
n/a
TRST
System Interface
DrvrInh1:2
dc
dc
n/a
n/a
n/a
n/a
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
12
8
Halt
dc
dc
dc
dc
n/a
n/a
n/a
n/a
10
n/a
n/a
n/a
n/a
1
n/a
n/a
n/a
12
n/a
n/a
n/a
8
async
RcvrInh
SysClk
SysErr
SysReset
TestEn
TmrClk
async
async
async
async
12
8
dc
dc
dc
dc
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
36
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
