Revision 1.02 – January 11, 2005
Data Sheet
Figure 1. PPC405CR Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Timers
MMU
PPC405
Processor Core
JTAG
8KB
D-Cache
DCU
Trace
ICU
16KB
I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
Arb
Code
Decompression
(CodePack™)
External
Bus
Controller
External
Bus Master
Controller
Processor Local Bus (PLB)
GPIO
IIC
UART
UART
Power
Mgmt
DCRs
DCR Bus
OPB
Bridge
SDRAM
Controller
13-bit addr
32-bit data
32-bit addr
32-bit data
The PPC405CR is designed using the IBM Microelectronics Blue Logic
®
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
™
Bus Architecture.
AMCC
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
