Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Spread Spectrum Clocking
Data Sheet
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC405CR the following conditions must be met:
•
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
•
•
The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see Note 1).
Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock
tracks the modulation.
•
Use the SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approx-
imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the
connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf-
fected by the modulation.
2. IIC operation is unaffected.
Caution: It is up to the system designer to ensure that any SSCG used with the PPC405CR meets the above
requirements and does not adversely affect other aspects of the system.
AMCC
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
