Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 3)
Ball
T17
T18
T19
T20
U1
Signal Name
GPIO5[TS3]
Ball
U18
U19
U20
V1
Signal Name
DQM0
Ball
V19
V20
W1
W2
W3
W4
W5
Signal Name
DQMCB
Ball
W20
Y1
Signal Name
IRQ6[GPIO23]
MemData15
UART0_RX
Reserved
BankSel3
MemData14
MemAddr11
HoldReq
UART0_RTS
EOT2/TC2
GND
GND
Y2
EOT3/TC3
ExtReq
Y3
PerData2
V2
MemAddr8
MemAddr6
UART1_RX
Y4
MemAddr4
UART1_TX
GND
U2
PerData0
V3
GND
Y5
U3
MemAddr10
V4
MemAddr9
Y6
UART1_RTS
U4
U5
U6
GND
V5
V6
V7
MemAddr7
W6
W7
W8
Y7
Y8
Y9
MemAddr0
MemData28
MemData24
[UART1_DTR]
ExtAck
MemAddr5
GPIO9[TrcClk]
MemAddr1
UART1_DSR
[UART1_CTS]
MemData29
U7
U8
MemAddr3
DQM3
V8
MemAddr2
MemData30
MemData26
ECC7
W9
MemData25
UART0_CTS
ECC6
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
DQM2
V9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
GND
U9
MemData31
MemData27
WE
V10
V11
V12
V13
V14
V15
V16
V17
V18
MemData23
ECC4
U10
U11
U12
U13
U14
U15
U16
U17
MemData22
GPIO8[TS6]
DQM1
ECC5
MemData20
GND
MemData21
UART0_DTR
ECC2
ECC3
MemData19
UART0_RI
Reserved
ECC0
UART0_TX
MemData16
IICSDA
MemData18
MemData17
ECC1
IICSCL
UART0_DSR
GND
GPIO6[TS4]
GND
GPIO7[TS5]
GND
GND
20
AMCC