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PPC405GPR-3KB400Z 参数 Datasheet PDF下载

PPC405GPR-3KB400Z图片预览
型号: PPC405GPR-3KB400Z
PDF下载: 下载PDF文件 查看货源
内容描述: Power PC的405GPr嵌入式处理器 [Power PC 405GPr Embedded Processor]
分类和应用: PC
文件页数/大小: 57 页 / 1081 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 2.04 – September 7, 2007  
405GPr – Power PC 405GPr Embedded Processor  
Data Sheet  
Serial Interface  
• One 8-pin UART and one 4-pin UART interface provided  
• Selectable internal or external serial clock to allow a wide range of baud rates  
• Register compatibility with NS16550 register set  
• Complete status reporting capability  
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode  
• Fully programmable serial-interface characteristics  
• Supports DMA using internal DMA engine  
IIC Bus Interface  
2
• Compliant with Philips® Semiconductors I C Specification, dated 1995  
• Operation at 100kHz or 400kHz  
• 8-bit data  
• 10- or 7-bit address  
• Slave transmitter and receiver  
• Master transmitter and receiver  
• Multiple bus masters  
• Supports fixed V IIC interface  
DD  
• Two independent 4 x 1 byte data buffers  
• Fifteen memory-mapped, fully programmable configuration registers  
• One programmable interrupt request signal  
• Provides full management of all IIC bus protocol  
• Programmable error recovery  
General Purpose IO (GPIO) Controller  
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master  
accesses  
• 23 of 24 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO  
capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:  
- 7 of 8 chip selects  
- All 13 external interrupts  
- All nine instruction trace pins  
• Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-  
stated if output bit is 1)  
12  
AMCC  
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