Revision 2.03 – September 7, 2007
405GP – Power PC 405GP Embedded Processor
Data Sheet
I/O Specifications—All speeds (Part 2 of 2)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
(TIS min)
(TIH min)
Internal Peripheral Interface
IICSCL
na
na
na
na
na
na
na
na
na
na
na
na
na
na
19
19
12
12
12
12
12
12
12
12
12
12
8
IICSDA
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
8
8
8
na
na
na
na
8
UART0_RTS
UART0_Rx
UART0_Tx
UART1_RTS/
UART1_DTR
UART1_DSR/
UART1_CTS
UART1_Rx
UART1_Tx
UARTSerClk
na
na
8
8
na
na
na
na
8
12
na
8
na
na
na
na
na
na
12
na
na
8
na
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK
12
8
na
na
12
na
na
na
na
8
async
async
async
async
async
TDI
TDO
TMS
na
na
TRST
System Interface
DrvrInh1:2
dc
dc
na
na
na
na
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
12
8
Halt
dc
dc
dc
dc
na
na
na
na
10
na
na
na
na
na
na
1
na
na
na
12
12
na
na
na
na
na
8
async
RcvrInh
SysClk
SysErr
SysReset
TestEn
TmrClk
async
async
async
async
8
dc
dc
dc
dc
na
na
na
na
52
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
