Revision 2.03 – September 7, 2007
405GP – Power PC 405GP Embedded Processor
Data Sheet
Signal Functional Description (Part 3 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
I/O
O
Type
Notes
SDRAM Interface
Memory data bus.
Notes:
MemData0:31
MemAddr12:0
3.3V LVTTL
3.3V LVTTL
1. MemData0 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
BA1:0
RAS
Bank Address supporting up to 4 internal banks.
Row Address Strobe.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
CAS
Column Address Strobe.
DQM for byte lane: 0 (MemData0:7),
1 (MemData8:15),
DQM0:3
O
3.3V LVTTL
2 (MemData16:23), and
3 (MemData24:31)
DQMCB
ECC0:7
BankSel0:3
WE
DQM for ECC check bits.
ECC check bits 0:7.
O
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Select up to four external SDRAM banks.
Write Enable.
O
ClkEn0:1
SDRAM Clock Enable.
O
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL
or zero-delay buffer.
MemClkOut0:1
O
3.3V LVTTL
External Slave Peripheral Interface
Peripheral data bus used by PPC405GP when not in external master
5V tolerant
3.3V LVTTL
mode, otherwise used by external master.
PerData0:31
I/O
1
Note: PerData0 is the most significant bit (msb) on this bus.
Peripheral address bus used by PPC405GP when not in external
master mode, otherwise used by external master.
Note: PerAddr0 is the most significant bit (msb) on this bus.
5V tolerant
PerAddr0:31
PerPar0:3
I/O
I/O
1
1
3.3V LVTTL
5V tolerant
3.3V LVTTL
Peripheral byte parity signals.
As outputs, these pins can act as byte-enables which are valid for an
entire cycle or as write-byte-enables which are valid for each byte on
each data transfer, allowing partial word transactions. As outputs,
pins are used by either the pripheral controller or the DMA controller
depending upon the type of transfer involved. Used as inputs when
an external bus master owns the external interface.
5V tolerant
PerWBE0:3
I/O
O
1, 7
3.3V LVTTL
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
or
5V tolerant
3.3V PCI
[PerWE]PCIINT
PCI interrupt. Open-drain output (two states; 0 or open circuit)
AMCC
37
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
