Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EX Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x3
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DCRs
NAND
Flash
Controller
EBC
EBM
IICx2/ SCP
BSC
UART
x2
GPIO
DCR
Bus
Power PC
405 Processor
(SPI)
Trace
16KB D-Cache 16KB I-Cache
JTAG
On-chip Peripheral Bus (OPB)
Arbiter
OPB/PLB
Bridges
GPT
PKA
TRNG
Processor Local Bus (PLB4)—128 bits
Arbiter
PCI-E
1-lane
PCI-E
1-lane
DDR1/2
SDRAM
AHB-PLB
Bridge
EIP-94
Security
DMA
MAL/w
Interrupt Coalescing
Controller
(4-Channel)
Controller
Feature
Ethernet
MAC
1Gbit
x2
USB 2.0
OTG
Controller
HSS
HSS
ULPI
The PPC405EX is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional
blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
