Part Number PPC405CR
Revision 1.02 – January 11, 2005
Data Sheet
PPC405CR
PowerPC 405CR Embedded Processor
Features
®
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DMA support for external peripherals, internal
UART and memory
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PowerPC 405 32-bit RISC processor core
operating up to 266MHz
- Scatter-gather chaining supported
- Four channels
- Memory Management Unit
- 16KB instruction and 8KB data caches
•
Programmable Interrupt Controller supports
interrupts from a variety of sources
- Multiply-Accumulate (MAC) function,
including fast multiply unit
- Supports 7 external and 10 internal interrupts
- Edge triggered or level-sensitive
- Positive or negative active
- Programmable Timers
•
•
Synchronous DRAM (SDRAM) interface oper-
ating up to 133MHz
- Non-critical or critical interrupt to processor
core
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
- Programmable critical interrupt priority
ordering
External Peripheral Bus
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•
•
•
•
Two serial ports (16550 compatible UART)
One IIC interface
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and
external peripherals
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
- Up to eight devices
Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
- External Mastering supported
Description
™
The PowerPC 405CR (PPC405CR) is a 32-bit RISC
embedded controller. High performance, peripheral
integration, and low cost make the device ideal for
wired communications, network printers, and other
computing applications.
The PPC405CR employs the IBM CoreConnect bus
architecture. This architecture, as implemented on the
PPC405CR, consists of a 64-bit, 133-MHz Processor
Local Bus (PLB) and a 32-bit, 66-MHz On-Chip
Peripheral Bus (OPB). High-performance peripherals
attach to the PLB and less performance-critical periph-
erals attach to the OPB.
This device is an easy upgrade for systems based on
PowerPC 403xx embedded processors, while provid-
ing a base for custom chip designs.
Technology: CMOS SA-12E 0.25 µm (0.18 µm L )
eff
The controller is powered by a PPC405 embedded
core. This core tightly couples a 266 MHz CPU, MMU,
instruction and data caches, and debug logic. Fine-
tuning of the core reduces data transfer overhead,
minimizes pipeline stalls, and improves performance.
Package: 27mm, 316-ball enhanced plastic ball grid
array (E-PBGA)
Power (estimated): Typical 0.8W, Maximum 2.0W at
200MHz.
AMCC
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
