Revision 1.02 – January 11, 2005
Data Sheet
SDRAM Memory Controller
The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of sys-
tem memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB
per bank are supported, up to a maximum of 1 GB. Memory timings, address and bank sizes, and memory
addressing modes are programmable.
Features include:
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11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
32-bit memory interface support
Programmable address compare for each bank of memory
Industry standard 168-pin DIMMS are supported (some configurations)
4MB to 256MB per bank
Programmable address mapping and timing
Auto refresh
Page mode accesses with up to 4 open pages
Power Management (self-refresh)
Error Checking and Correction (ECC) support
- Standard SEC/DED coverage
- Aligned nibble error detect
- Address error logging
External Peripheral Bus Controller (EBC)
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Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripheral I/O
Up to 66MHz operation
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus width support
Programmable 2K clock time-out counter with disable for Ready
Programmable access timing per device
- 0–255 wait states for non-burst devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
Programmable address mapping
Peripheral device pacing with external “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
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DMA Controller
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Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
AMCC
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
