Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 16. Strapping Pin Assignments (Sheet 2 of 2)
Function
Option
Ball Strapping
External Bus Divider from PLB2, 3
C17
P18
GPIO3[TS1O] GPIO4[TS2O]
Divide by 2
Divide by 3
Divide by 4
Divide by 5
0
0
1
1
0
1
0
1
ROM Width
W6
Y5
UART1_RTS/
UART1_DTR
UART1_Tx
8-bit ROM
16-bit ROM
32-bit ROM
Reserved
0
0
1
1
0
1
0
1
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405CR. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405CR, visit the technical
documents area of the AMCC PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
Specifications” on page 32. Further requirements are detailed in the Clocking chapter of the PowerPC 405CR Embedded Processor
User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
40
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
