Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
Description
I/O
Type
Notes
External Master Peripheral Interface
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
PerClk
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
O
O
I
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
Hold Request, used by an external master to request ownership of
the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
6
Hold Acknowledge, used by the PPC405CR to transfer ownership of
peripheral bus to an external master.
5V tolerant
3.3V LVTTL
O
I
ExtReq is used by an external master to indicate it is prepared to
transfer data.
5V tolerant
3.3V LVTTL
1
5V tolerant
3.3V LVTTL
ExtAck is used by the PPC405CR to indicate a data transfer cycle.
O
I
6
Used by an external master to indicate the priority of a given external
master tenure.
5V tolerant
3.3V LVTTL
HoldPri
BusReq
PerErr
1
Used when the PPC405CR needs to regain control of the peripheral
interface from an external master.
5V tolerant
3.3V LVTTL
O
I
Used as an input to indicate that an external slave peripheral error
has occurred.
5V tolerant
3.3V LVTTL
1, 5
Internal Peripheral Interface
Serial clock. Used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
individually connected to either UART.
5V tolerant
3.3V LVTTL
UARTSerClk
I
1
5V tolerant
3.3V LVTTL
UART0_Rx
UART0_Tx
UART0 Receive (serial data in).
UART0 Transmit (serial data out).
UART0 Data Carrier Detect.
UART0 Data Set Ready.
I
O
I
1
6
1
1
1
6
6
1
1
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
O
O
I
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART1_Rx
UART1 Receive (serial data in).
I
AMCC
25
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
