欢迎访问ic37.com |
会员登录 免费注册
发布采购

PPC405GPR3KB333 参数 Datasheet PDF下载

PPC405GPR3KB333图片预览
型号: PPC405GPR3KB333
PDF下载: 下载PDF文件 查看货源
内容描述: [32-BIT, 333.33 MHz, RISC PROCESSOR, PBGA456, 27 X 27 MM, LEAD FREE, PLASTIC, EBGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 58 页 / 1211 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号PPC405GPR3KB333的Datasheet PDF文件第50页浏览型号PPC405GPR3KB333的Datasheet PDF文件第51页浏览型号PPC405GPR3KB333的Datasheet PDF文件第52页浏览型号PPC405GPR3KB333的Datasheet PDF文件第53页浏览型号PPC405GPR3KB333的Datasheet PDF文件第54页浏览型号PPC405GPR3KB333的Datasheet PDF文件第56页浏览型号PPC405GPR3KB333的Datasheet PDF文件第57页浏览型号PPC405GPR3KB333的Datasheet PDF文件第58页  
Revision 2.00 – December 2, 2004  
405GPr – Power PC 405GPr Embedded Processor  
Data Sheet  
PPC405GPr New Mode Strapping Pin Assignments (Sheet 3 of 3)  
Function  
Option  
Ball Strapping  
PCI Asynchronous Mode  
Enable  
Y3  
ExtAck  
Synchronous PCI Mode  
Asynchronous Mode  
0
1
External Bus Synchronous  
Mode Enable 3  
A22  
GPIO3[TS1O]  
Asynchronous Mode  
Synchronous Mode  
0
1
PCI Arbiter Enable 3  
AF18  
GPIO4[TS2O]  
Internal Arbiter Disabled  
Internal Arbiter Enabled  
0
1
New Mode Enable  
In Legacy mode the  
PPC405GPr functions like the  
PPC405GP.  
If not strapped, the PPC405GPr  
defaults to Legacy mode.  
D20  
GPIO24  
Legacy (PPC405GP) mode  
New (PPC405GPr) mode4  
0
1
Flip Circuit Disable  
AB3  
(must be strapped low (0)  
GPIO9[TrcClk]  
during initilization).  
Normal operation  
0
Note:  
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the  
PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as  
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical  
documents area of the AMCC PowerPC web site.  
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking  
Specifications” on page 43. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor  
User’s Manual.  
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using  
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.  
4. The pull-up initialization strapping resistor must be 1krather than 3kin order to overcome the internal pull-down resistor.  
Revision Log  
Date  
Contents of Modification  
400MHz part numbers and new power/current numbers  
03/13/2003  
08/28/2003  
Add new VDD values for 400MHz parts.  
Correct package drawings and add lead-free part numbers.  
Add +105°C temperature specification.  
11/22/2004  
12/02/2004  
Add 1 ms. voltage ramp-up restriction.  
Update to AMCC format.  
AMCC  
55  
 复制成功!