Revision 2.00 – December 2, 2004
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
Signal Functional Description (Sheet 6 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
UART1_Tx
UART1 Serial Data Out.
O
6
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must toggle
a DCR bit.
UART1_DSR/
UART1_CTS
5V tolerant
I
1
6
3.3V LVTTL
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR bit.
UART1_RTS/
UART1_DTR
5V tolerant
3.3V LVTTL
O
5V tolerant
IICSCL
IIC Serial Clock.
IIC Serial Data.
I/O
I/O
1, 2
1, 2
3.3V LVTTL
5V tolerant
3.3V LVTTL
IICSDA
Interrupts Interface
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
5V tolerant
3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
1
JTAG Interface
5V tolerant
TDI
Test data in.
I
I
1, 4
1, 4
3.3V LVTTL
5V tolerant
3.3V LVTTL
TMS
TDO
TCK
JTAG test mode select.
Test data out.
5V tolerant
3.3V LVTTL
O
I
JTAG test clock. The frequency of this input can range from DC to
25MHz.
5V tolerant
3.3V LVTTL
1, 4
5
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405GPr.
5V tolerant
3.3V LVTTL
TRST
System Interface
SysClk
I
5V tolerant
3.3V LVTTL
Main system clock input.
I
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
5V tolerant
3.3V LVTTL
SysReset
I/O
1, 2
AVDD
Clean voltage input for the PLL.
Clean Ground input for the PLL.
I
I
AGND
5V tolerant
SysErr
Halt
Set to 1 when a Machine Check is generated.
Halt from external debugger.
O
I
3.3V LVTTL
5V tolerant
3.3V LVTTL
1, 2
AMCC
35
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
