Revision 2.00 – December 2, 2004
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
PPC405GPr New Mode Strapping Pin Assignments (Sheet 2 of 3)
Function
Option
Ball Strapping
PLL Feedback Divider 2, 3
B14
DMAAck2
C12
DMAAck3
AF5
GPIO7[TS5]
AC7
GPIO8[TS6]
Divide by 16
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Divide by 9
Divide by 10
Divide by 11
Divide by 12
Divide by 13
Divide by 14
Divide by 15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OPB Divider from PLB 2
L25
EMCTxD1
J26
EMCTxD0
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
PCI Divider from PLB 2, 3
D18
GPIO1[TS1E]
C20
GPIO2[TS2E]
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
External Bus Divider from
PLB 2
K25
EMCTxErr
K23
EMCTxEn
Divide by 2
Divide by 3
Divide by 4
Divide by 5
0
0
1
1
0
1
0
1
ROM Width
AD2
UART1_RTS/
UART1_DTR
AC2
UART1_Tx
8-bit ROM
16-bit ROM
32-bit ROM
Reserved
0
0
1
1
0
1
0
1
ROM Location
U2
HoldAck
PPC405GPr Peripheral Attach
PPC405GPr PCI Attach
0
1
54
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
