Revision 2.00 – December 2, 2004
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
I/O Specifications—Group 1 (Sheet 3 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
(TIS min)
(TIH min)
Trace
[TS1E]
[TS2E]
[TS1O]
[TS2O]
[TS3]
10pFload
on
clk/data
PTC/2+0.7
PTC/2-0.5
na
na
10.3
7.1
TrcClk
[TS4]
[TS5]
[TS6]
AMCC
49
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
