Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Table 16. I/O Specifications—416 MHz CPU
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
2. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
External Peripheral Interface
PerClk
na
na
na
na
19.1
19.1
8.7
8.7
na
na
CRAM_Clk
PerClk/
CRAM_Clk
CRAM_AdV
PerAddr04:31
BusReq
na
na
na
na
1.6
1.6
na
1.6
na
1.6
na
na
na
na
na
na
2.1
2.1
na
2.1
na
2.1
na
na
7.2
7.35
7.3
7.3
7.5
na
2
19.1
19.1
19.1
19.1
19.1
na
8.7
8.7
8.7
8.7
8.7
na
PerClk/
CRAM_Clk
2.16
2.1
2.1
2.1
na
PerClk/
CRAM_Clk
PerClk/
CRAM_Clk
PerCS0:7
PerData00:31
HoldReq
HoldAck
HoldPri
PerClk/
CRAM_Clk
PerClk/
CRAM_Clk
PerClk/
CRAM_Clk
7.3
na
2.1
na
19.1
na
8.7
na
PerClk/
CRAM_Clk
PerClk/
CRAM_Clk
PerOE
7.35
na
2.15
na
19.1
na
8.7
na
PerClk/
CRAM_Clk
PerReady
PerRW
PerClk/
CRAM_Clk
7.35
7.3
7.1
7.1
7.1
7.1
2.15
2.15
0.9
0.9
0.9
0.9
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
PerClk/
CRAM_Clk
PerWBE0:3
NFALE
PerClk/
CRAM_Clk
PerClk/
CRAM_Clk
NFCE0
PerClk/
CRAM_Clk
NFCLE
PerClk/
CRAM_Clk
NFData0:7
NFRB
9.2
10
-0.7
0
PerClk/
CRAM_Clk
PerClk/
CRAM_Clk
NFRE
7.1
0.9
PerClk/
CRAM_Clk
NFWE
7.1
7.3
0.9
2.1
DMAAck
na
5
na
19.1
19.1
19.1
8.7
8.7
8.7
DMAEOT/TC
DMAReq
0.9
na
na
50
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
