Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Initialization
Preliminary Data Sheet
The following describes the method by which initial chip settings are established when a system reset occurs.
Strapping
When the SysReset input is driven low (system reset), the state of certain I/O pins is read in order to enable default
initial conditions before PPC405EZ start-up. The actual instant of capture is the nearest system clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V, or 10kΩ to +5V. The
recommended pull-down is 1KΩ to GND. These pins are only used for strap functions during reset. They are used
for other signals during normal operation. The following table lists the strapping pins along with their functions and
strapping options. The signal names assigned to the pins for normal operation appear below the pin number.
Table 17. Strapping Pin Assignments
Pin Strapping
F03
(GPIO114)
E03
(GPIO112)
D01
(GPIO111)
D02
(GPIO110)
Function
Option
8 bits wide
16 bits wide
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Initialize from EBC
32 bits wide
512 page, 3 addr cycle
512 page, 4 addr cycle
2K page, 4 addr cycle
2K page, 5 addr cycle
Slow
Initialize from NAND Flash
Initialize from SPI
Reserved
Fast
na
Initialize from IIC
Note: If reading of initialization data from
the IIC interface fails, the PPC405EZ
defaults to strapping option 0010.
na
AMCC Proprietary
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
