Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Ratings and Specifications
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Supply Voltage (Internal Logic)
Symbol
Value
0 to +1.6
0 to +3.6
0 to +3.6
0 to +1.6
0 to +3.465
0 to +3.465
0 to +3.6
0 to +5.5
-55 to +150
-40 to +120
+125
Unit
V
Notes
VDD
OVDD
OVDD
1
2
Non-EBC I/O Supply Voltage
EBC I/O Supply Voltage
V
V
3
PLL_AVDD
ADC_AVDD
DAC_AVDD
VIN
PLL Analog Supply Voltage
ADC Analog Supply Voltage
DAC Analog Supply Voltage
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
Case temperature under bias
Junction temperature
V
V
V
V
VIN
V
TSTG
°C
°C
°C
TC
TJMax
1. All voltages are specified with respect to GND.
2. The analog voltages use for the system PLL, the ADC, and the DAC can be derived from VDD and OVDD1, but must be filtered
as shown below before entering the PPC405EZ. Use a separate filter for each voltage. The maximum value for ADC_PLL and
DAC_PLL must be limited to the values shown in this table.
3. OVDD2 must be limited to a maximum value of +3.3V if CRAM/PSRAM devices are attached to the EBC interface. This is a
limitation imposed by the CRAM/PSRAM devices, not the PPC405EZ.
V
PLL_AV
DD
L1 – Murata BLM18AG121SN1D
DD
L1
C1 – 0.1 μF ceramic
C1
PLL_AGND
GND
OV
1
ADC_PLL, DAC_PLL
L1 – Murata BLM18AG121SN1D
C1 – 0.1 μF ceramic
DD
L1
C2
C1
C2 – 0.01μF ceramic
ADC_GND, DAC_GND
GND
AMCC Proprietary
41
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
