Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Signal Functional Descriptions
The following table provides a description of the I/O signals on the PPC405EZ.
Table 6. Signal Functional Description (Sheet 1 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Ethernet Interface
EMCCOL
Description
I/O
Type
Notes
Collision signal from the PHY.
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5
5
EMCCRS
Carrier sense signal from the PHY.
EMCMDC
Management data clock to the PHY.
O
I/O
EMCMDIO
Management data I/O between the Ethernet controller and the PHY.
3.3V LVTTL
Rcvr
EMCRxClk
EMCRxDV
EMCRxEr
Input receive clock from the PHY.
Receive data valid.
I
I
I
3.3V LVTTL
5
5
3.3V LVTTL
Rcvr
Receive error from the PHY.
Receive data from the PHY.
EMCRxD3 is the msb.
EMCRxD0:3
EMCTxClk
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Input transmit clock from the PHY.
Transmit data to the PHY.
EMCTxD3 is the msb.
EMCTxD0:3
O
EMCTxEn
EMCTxEr
Transmit enable.
O
O
3.3V LVTTL
3.3V LVTTL
Transmit error to the PHY.
IEEE 1588 Network Synchronization Interface
IEEE_1588TS
IIC Peripheral Interface
IIC0SClk
Test signal.
O
3.3V LVTTL
IIC Serial Clock.
IIC Serial Data.
I/O
I/O
3.3V IIC
3.3V IIC
1, 5
1, 5
IIC0SData
Interrupts Interface
IRQ0:4
Interrupt requests.
Test clock.
I
3.3V LVTTL
1, 5
JTAG Interface
3.3V LVTTL
Rcvr w/pull-up
TCK
I
5
5
TDI
Test data in.
I
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
TDO
TMS
Test data out.
Test mode select.
5
5
Test reset. Must be low at power-on to initialize the JTAG controller
and for normal operation of the PPC405EZ.
3.3V LVTTL
Rcvr w/pull-up
TRST
I
AMCC Proprietary
35
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
