PPC405EXr – PowerPC 405EXr Embedded Processor
Revision 1.10 - July 10, 2008
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EXr Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x3
Clock
Control
Reset
Power
Mgmt
Timers
MMU
Power PC
405 Processor
JTAG
Trace
DCRs
UART
x2
IICx2/
BSC
SCP
(SPI)
GPIO
NAND
Flash
Controller
EBC
EBM
DCR
Bus
Arbiter
On-chip Peripheral Bus (OPB)
16KB D-Cache 16KB I-Cache
OPB/PLB
Bridges
GPT
PKA
TRNG
Arbiter
Processor Local Bus (PLB4)—128 bits
DDR1/2
SDRAM
Controller
EIP-94
Security
Feature
PCI-E
1-lane
DMA
Controller
(4-Channel)
MAL/w
Interrupt Coalescing
AHB-PLB
Bridge
HSS
Ethernet
MAC
1Gbit
USB 2.0
OTG
Controller
ULPI
The PPC405EXr is designed using the IBM Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
