Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
• Seven external and 29 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Selectable non-critical or critical interrupt requests to the PPC405 processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector generation for reduced latency interrupt handling
10/100 Mbps Ethernet MAC
• Two units capable of full- and half-duplex, 10 Mbps or 100 Mbps operation
• Integrated ZMII Bridge supports use of MII, SMII or RMII connections to external PHYs (PHYs not
included on chip)
- Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for one to
two PHY applications
- Media Independent Interface (MII) for single or dual PHY applications
• Dedicated media access layer (MAL) provides DMA support
JTAG
• IEEE 1149.1 Test Access Port
• Debugger support
• JTAG boundary scan support (BSDL file available)
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
