Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
Table 15. I/O Specifications—133 and 200MHz (Sheet 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(maximum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay Hold Time
(TIS min)
(TIH min)
(TOV max)
(TOH min)
SDRAM Interface
BA1:0
n/a
n/a
n/a
n/a
n/a
n/a
2.7
n/a
2.8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1.0
n/a
1.0
n/a
n/a
7.1
5.2
6.8
4.5
5.3
5.3
5.2
7.0
5.2
6.7
5.5
1.1
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.9
1.5
19
19
19
40
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
2, 3
3
BankSel3:0
CAS
2, 3
3
ClkEn0:1
DQM0:3
3
DQMCB
3
ECC0:7
3
MemAddr12:00
MemData00:31
RAS
2, 3
3
2, 3
2, 3
WE
External Slave Peripheral Bus Interface
[DMAReq0:3]
[DMAAck0:3]
[EOT0:3/TC0:3]
PerAddr04:31
PerBLast
[4.7]
n/a
[4.5]
3.0
4.2
n/a
n/a
5.7
n/a
3.4
4.5
7.6
3.0
n/a
2.9
[0.0]
n/a
[0.0]
1.0
0.0
n/a
n/a
1.0
n/a
0.0
0.0
0.0
0.0
n/a
0.0
n/a
[8.5]
[8.6]
8.5
n/a
[1.0]
[1.0]
1.0
n/a
12
12
17
12
12
12
17
12
17
12
n/a
12
17
n/a
n/a
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
8
11
8
7.1
1.2
PerCS0
8.7
1.0
8
[PerCS1:7]
PerData00:31
PerOE
[8.7]
9.5
[1.0]
1.3
8
11
8
7.5
1.3
PerPar0:3
PerR/W
8.9
1.1
11
8
7.5
1.2
PerReady
PerWBE0:3
PerClk
n/a
n/a
n/a
8
7.7
1.3
-0.6
n/a
-0.7
n/a
11
n/a
5
PerErr
External Master Peripheral Bus Interface
BusReq
n/a
n/a
4.5
n/a
n/a
2.9
4.0
n/a
n/a
0.0
n/a
n/a
0.0
0.0
6.8
6.9
n/a
8.0
7.3
n/a
n/a
1.2
1.2
n/a
0.0
1.4
n/a
n/a
12
12
8
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
ExtAck
ExtReq
n/a
19
n/a
12
8
ExtReset
HoldAck
12
HoldPri
n/a
n/a
n/a
n/a
HoldReq
IIC EEPROM Controller
IECSCL
aysnc
aysnc
aysnc
aysnc
aysnc
aysnc
aysnc
aysnc
17
17
11
11
IECSDA
64
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
