Part Number NPe405H
Revision 1.01 – April 18, 2007
Data Sheet
NPe405H
PowerNP NPe405H Embedded Processor
- Programmable critical interrupt priority ordering
- Programmable critical interrupt vector
Programmable timers
FEATURES
™
•
PowerNP technology using an AMCC Pow-
•
•
•
•
•
•
®
erPC 405 32-bit RISC processor core operat-
Two serial ports (16550 compatible UART)
One IIC interface
ing up to 266 MHz
•
PC-133 synchronous DRAM (SDRAM) inter-
face
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
- 32-bit interface for non-ECC applications
Internal processor local bus (PLB) runs at
SDRAM interface frequency
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
•
•
Supports PowerPC processor boot from PCI
memory
•
External bus for peripheral devices
- Flash and ROM interface
User accessible performance counters
- Direct support for 8-, or 16-, or 32-bit SRAM
and external peripherals
DESCRIPTION
- Up to 8 devices
Designed specifically to address embedded applica-
tions, the NPe405H provides a high-performance, low-
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power manage-
ment features and lower power dissipation
requirements.
- External mastering supported
•
•
DMA support for external peripherals, internal
UARTs and memory
- Scatter-gather chaining supported
- Four channels
PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
This chip contains a high-performance RISC proces-
sor core, SDRAM controller, PCI bus bridge, Ethernet
EMACs, HDLC controllers, external bus controller for
ROM, Flash, and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general pur-
pose I/O.
- Asynchronous PCI bus interface
- Internal PCI bus arbiter which can be dis-
abled for use with an external arbiter
•
•
Four 10/100 Ethernet MACs supporting up to
four external PHYs via MII, RMII, or SMII inter-
faces
Technology: CMOS SA-12E 0.25 µm
(0.18 µm L )
Package: 35mm, 580-ball enhanced plastic ball grid
array (E-PBGA)
Power (typical): 2.3W at 133MHz, 2.9W at 200MHz,
3.4W at 266MHz
eff
HDLC interface with 32 channels through two
ports at up to 4.096 Mbps each or 8.192 Mbps
for a single port
•
•
HDLC interface with 8 channels through 8
ports at 2.048 Mbps maximum
Programmable interrupt controller
- Seven external and 49 internal
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
AMCC Proprietary
DS2011
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
