Data Sheet
NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM
Figure 1. NPe405H Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x2
Clock
Control
Reset
Timers
MMU
Power
Mgmt
DCRs
See Peripheral Interface
PPC405
Processor Core
JTAG
8KB
D-Cache
DCU
Trace
ICU
DCR Bus
GPIO
x2
IIC IEC
UART
x2
16KB
I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
Ethernet
x4
MAL0
MAL1
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
External
Bus Master
Controller
PCI Bridge
HDLCEX
MAL2
HDLCMP
ZMII
32-bit addr
32-bit data
66 MHz max (async)
Two
32-channel
ports
8
MII, RMII,
single-channel
ports
SMII
The NPe405H is designed using the IBM Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to
generate complex ASICs using IBM CoreConnect™ Bus Architecture.
6
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
