Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 9 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
System Interface
Description
I/O
Type
Notes
3.3V Analog
Wire w/ESD
SysClk
SysReset
SysErr
Main System Clock input.
I
I/O
O
5V tolerant
3.3V LVTTL
Main System Reset.
1, 2
5V tolerant
3.3V LVTTL
Set to 1 when a Machine Check is generated.
Halt from external debugger.
5V tolerant
3.3V LVTTL
Halt
I
1
5V tolerant
3.3V LVTTL
GPIO0_00:31
GPIO1_00:31
TestEn
System General Purpose I/O.
I/O
I/O
I
5V tolerant
3.3V LVTTL
Communications General Purpose I/O.
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
3.3V LVTTL
Rcvr w/PD
This input must toggle at a rate of less than one half the CPU
core frequency (less than 100MHz in most cases). In most
cases this input toggles much slower (in the 1MHz to 10MHz
range).
5V tolerant
3.3V LVTTL
TmrClk
I
1
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status.To access this function, software
must toggle a DCR bit.
5V tolerant
3.3V LVTTL
O
O
O
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
5V tolerant
3.3V LVTTL
Trace Status. To access this function, software must toggle a
DCR bit.
5V tolerant
3.3V LVTTL
[TS3:6]
[TrcClk]
Trace interface clock. A toggling signal that is always half of
the CPU core frequency. To access this function, software
must toggle a DCR bit.
5V tolerant
3.3V LVTTL
O
1
Power Pins
Ground
GND
I
Hardwire
Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, and
P09-P14 are also thermal balls.
VDD
Logic voltage—2.5V
I
I
Hardwire
Hardwire
OVDD
Output driver voltage—3.3V
3.3V DC
AVDD
Filtered PLL voltage—2.5V
I
Wire w/ESD
Other Pins
Reserved
Do not connect signals, voltage, or ground to these pins.
n/a
n/a
AMCC Proprietary
DS2011
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
