Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs.
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to NPe405L start-up. The actual capture instant is the nearest SysClk edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to +5V,
the recommended pull-down is 1kΩ to GND.These pins are used for strap functions only during reset. They
are used for other signals during normal operation. The following table lists the strapping pins along with their
functions and strapping options.
Strapping Pin Assignments
Function
Option
Ball Strapping
Y21
EXT_BootW
(UART1_Tx)
Width of boot device on EBC data bus
8 bits
0
1
16 bits
ZMII_Mode
V21
U20
Ethernet ZMII mode
(UART1_RTS) (UART1_DTR)
MII mode
0
0
1
1
0
1
0
1
SMII mode
RMII 10 Mbps mode
RMII 100 Mbps mode
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
