Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Clocking Specifications
Symbol
Parameter
Min
Max
Units
SysClk Input
F
T
SysClk clock input frequency
25
15
66.66
40
MHz
ns
C
C
SysClk clock period
T
T
Clock edge stability (phase jitter, cycle to cycle)
Clock input high time
0.15
ns
CS
CH
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
T
Clock input low time
ns
CL
Note: Input slew rate > 2V/ns
MemClkOut Output
F
T
F
T
F
T
MemClkOut clock output frequency–133MHz
MemClkOut clock period–133MHz
MemClkOut clock output frequency–200MHz
MemClkOut clock period–200MHz
MemClkOut clock output frequency–266MHz
MemClkOut clock period–266MHz
Clock output high time
66.66
MHz
ns
C
C
C
C
C
C
15
100
MHz
ns
10
133.33
MHz
ns
7.5
T
45% of nominal period 55% of nominal period
45% of nominal period 55% of nominal period
ns
CH
T
Clock output low time
ns
CL
Other Clocks
F
VCO frequency
400
800
66.66
100
MHz
MHz
MHz
MHz
MHz
MHz
MHz
C
F
PLB frequency–133MHz
PLB frequency–200MHz
PLB frequency–266MHz
OPB frequency–133MHz
OPB frequency–200MHz
OPB frequency–266MHz
C
F
C
F
133.33
C
1
F
50
C
F
50
C
1
F
50
C
Notes:
1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.
Clocking Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
42
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
