Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
I/O Specifications—133 and 200MHz (Part 1 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L
IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and
reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(maximum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay Hold Time
(T min)
T
min)
(T max)
(T min)
IS
IH
OV
OH
Ethernet Interface
EMC0MDClk
n/a
n/a
n/a
7.4
8.8
1.5
1.2
12
12
8
8
1, async
1
EMC0MDIO
n/a
EMC0MDClk
PHYTX
EMC0TxD0:3
[EMC0Tx0:1D0:1]
[EMC0Tx0:1D]
10.5
[7.3]
[5.0]
3.0
[2.3]
[1.7]
n/a
n/a
12
12
8
8
1
1
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
11.8
[7.2]
[5.6]
2.9
[2.3]
[1.7]
n/a
n/a
n/a
n/a
PHYTX
PHYTX
EMC0TxErr[EMC0Tx1En]
PHY0Col[PHY0Rx1Er]
PHY0CrS[PHY0CrS0DV]
PHY0RxClk
11.8[7.4]
n/a
2.9[2.4]
n/a
12
n/a
n/a
n/a
8
1
async[0.2] async[1.7]
async[0.1] async[1.9]
n/a
n/a
n/a
1
1
n/a
n/a
n/a
n/a
n/a
n/a
1, async
PHY0RxD0:3
1.5
1.7
[PHY0Rx0:1D0:1]
[PHY0Rx0:1D]
[0.8]
[0.9]
[1.7]
[0.3]
n/a
n/a
n/a
n/a
PHYRX
1
PHY0RxDV[PHY0CRS1DV]
PHY0RxErr[PHY0Rx0Er]
PHY0TxClk[PHY0RefClk]
HDLCEX Interface
HDLCEXRxClk
1.3[0.7]
1.3[0.7]
n/a
1.7[1.7]
1.8[1.9]
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
PHYRX
PHYRX
1
1
1, async
n/a
23.8
24.2
n/a
n/a
2.1
1.1
n/a
n/a
1.0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
3.3
n/a
3.5
3.8
n/a
n/a
n/a
n/a
12
n/a
n/a
n/a
n/a
8
HDLCEXRxDataA:B
HDLCEXRxFS
n/a
HDLCEXTxClk
n/a
HDLCEXTxDataA:B
HDLCEXTxFS
n/a
10.5
n/a
20.3
n/a
n/a
12
n/a
8
[HDLCEXTxEnA]
[HDLCEXTxEnB]]
Trace Interface
[TrcClk]GPIO00
11.3
11.8
n/a
12
8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11.2
7.0
7.0
6.5
6.4
6.4
1.2
1.2
1.2
1.0
1.0
1.0
12
12
12
12
12
12
8
8
8
8
8
8
[TS1E]GPIO01
[TS2E]GPIO02
[TS1O]GPIO03
[TS2O]GPIO04
[TS3:6]GPIO05:08
47
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
