Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Max
2.5
–
Units
MHz
ns
EMC0MDClk output frequency
EMC0MDClk period
–
400
EMC0MDClk output high time
EMC0MDClk output low time
PHY0TxClk input frequency
PHY0TxClk period
160
–
ns
160
–
ns
2.5
25
400
–
MHz
ns
40
PHY0TxClk input high time
PHY0TxClk input low time
PHY0RxClk input frequency
PHY0RxClk period
35% of nominal period
ns
35% of nominal period
–
ns
2.5
25
400
–
MHz
ns
40
PHY0RxClk input high time
PHY0RxClk input low time
PerClk output frequency–133MHz
PerClk period–133MHz
35% of nominal period
ns
35% of nominal period
–
ns
–
30
–
33.33
–
MHz
ns
PerClk output frequency–200MHz
PerClk period–200MHz
50
–
MHz
ns
20
–
PerClk output frequency–266MHz)
PerClk period–266MHz
66.66
–
MHz
ns
15
PerClk output high time
45% of nominal period 55% of nominal period
45% of nominal period 55% of nominal period
ns
PerClk output low time
ns
1000/(2T
+ 2ns)
–
MHz
ns
UARTSerClk input frequency (Note 1)
UARTSerClk period
OPB
–
2T
T
+ 2
+ 1
+ 1
OPB
UARTSerClk input high time
–
ns
OPB
T
UARTSerClk input low time
TmrClk input frequency–133MHz
TmrClk period–133MHz
TmrClk input frequency–200MHz
TmrClk period–200MHz
TmrClk input frequency–266MHz
TmrClk period–266MHz
TmrClk input high time
–
ns
MHz
ns
OPB
–
33.33
30
–
–
50
MHz
ns
20
–
–
66.66
–
MHz
ns
15
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
TmrClk input low time
ns
HDLCEXTxClk, HDLCEXRxClk
Notes:
0
8.192
MHz
1. T
is the period in ns of the OPB clock. The maximum OPB clock frequency is 33.33 MHz for 133MHz parts, 50 MHz for
OPB
200MHz parts, and 66.66MHz for 266MHz parts.
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