Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
NPe405L Embedded Controller Functional Block Diagram
Clock
Control
Reset
Universal
Interrupt
Controller
x2
Power
Mgmt
See Peripheral Interface
Clock Timing table
DCRs
Timers
MMU
UART
x2
PPC405
Processor Core
GPIO
IIC
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
8KB
D-Cache
On-chip Peripheral Bus (OPB)
Arb
DMA
OPB
Bridge
Controller
(4-Channel)
Processor Local Bus (PLB)
Ethernet
MAL0
x2
MAL1
HDLCEX
External
Bus
Controller
SDRAM
Controller
ZMII
28-bit addr
16-bit data
13-bit addr
32-bit data
MII,
RMII,
SMII
Two
32-channel
ports
The NPe405L is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way
to generate complex ASICs using IBM CoreConnect Bus Architecture.
Address Map Support
The NPe405L incorporates two separate address maps. The first is a fixed processor address map that
serves the PowerPC family of processors. This address map defines the possible contents of various address
regions which the processor can access. The second address map is for Device Configuration Registers
(DCRs). The DCRs are accessed by software running on the NPe405L processor through the use of mtdcr
and mfdcr commands.
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
