Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
NPe405L Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x2
Clock
Control
Reset
Timers
MMU
PPC405
Processor Core
JTAG
8KB
D-Cache
DCU
Trace
ICU
16KB
I-Cache
Arb
On-chip Peripheral Bus (OPB)
GPIO
IIC
UART
x2
Power
Mgmt
DCRs
See Peripheral Interface
Clock Timing table
DCR Bus
DMA
Controller
(4-Channel)
OPB
Bridge
Processor Local Bus (PLB)
Ethernet
x2
HDLCEX
MAL0
MAL1
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
28-bit addr
16-bit data
ZMII
Two
32-channel
ports
MII,
RMII,
SMII
The NPe405L is designed using the IBM Microelectronics Blue Logic
methodology in which major functional
blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way
to generate complex ASICs using IBM CoreConnect
Bus Architecture.
Address Map Support
The NPe405L incorporates two separate address maps. The first is a fixed processor address map that
serves the PowerPC family of processors. This address map defines the possible contents of various address
regions which the processor can access. The second address map is for Device Configuration Registers
(DCRs). The DCRs are accessed by software running on the NPe405L processor through the use of
mtdcr
and
mfdcr
commands.
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
