Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
Figures 2 and 3 define the conditions under which timing measurements are made. The user designs must guaran-
tee that minimum timings are met with maximum clock skew rate (fastest edge) and voltage swing.
Figure 2. PCI Signal Output Timing
PCI CLK
1.5
t5
OUTPUT
1.5
DELAY
TRI-STATE
1.5
1.5
OUTPUT
t6
t7
Figure 3. PCI Signal Input Timing
PCI CLK
INPUT
t8
t9
INPUTS VALID
146
DS1656
AMCC Confidential and Proprietary