Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
TIMING SPECIFICATION
PCI Clock Specification
Table 5 summarizes the A.C. characteristics for the PCI bus signals as they apply to the S5320. The figures after
Table 5 visually indicate the timing relationships.
Table 5. Functional Operation Range
(V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN)
CC
Symbol
Parameter
Min
Max
Units
Notes
T
30
-
ns
Clock Time
cyc
t
t
t
t
11
11
1
-
-
ns
ns
CLK High Time
CLK Low Time
Rise Time (0.2V
Fall Time (0.6V
1
2
3
4
4
4
V/ns
V/ns
ns
to 0.6V
load)
CC
1
1
CC
1
to 0.2V
load)
CC
CC
CLK to Signal Valid Delay (Bused Signals)
CLK to Signal Valid Delay (Point-to-Point Signals)
2
2
11
12
t
1,2
5
t
t
t
t
2
-
-
28
-
ns
ns
ns
ns
Float to Active Delay
3
3
4
4
6
7
8
9
Active to Float Delay
7
0
Rising Edge Setup
-
Hold from PCI Clock Rising Edge
Notes:
1. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion
of the clock waveform as shown in Figure 1.
2. Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load.
3. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the com-
ponent pin is less than or equal to the leakage current specification.
4. See the timing measurement conditions in Figure 3.
Figure 1. PCI Clock Timing
t1
t4
t3
0.6VCC
0.2VCC
0.6VCC
0.2VCC
VIH2
t2
TCL
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