Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Clock 2: The Add-On logic has sampled PTATN# and
PTBURST# active, indicating that at least two read
data transfers are requested by the PCI. The Add-On
will start servicing the Burst Read transfer by first read-
ing the Pass-Thru Address via PTADR#. This is an
asynchronous read, meaning that the address will
appear on DQ after a propagation delay from the
assertion of PTADR#. In the event that the address is
not required, this cycle and the next could be skipped
(as the next clock provides a turn-around cycle).
deasserts PTBURST#, indicating that the previus read
was the second to last. The next transfer from the
Add-On will be the last. The PTBE# outputs are
updated to indicate which bytes are valid for the last
transfer. The Add-On logic samples PTBURST#
asserted, so it knows more data is being requested.
However, it is not ready to transfer data yet, so it deas-
serts PTRDY# and WR#. The data on the DQ bus is a
donÕt care, as the Add-On is not writing during this
cycle. The DQ bus could be in tri-state.
Clock 3: The Add-On logic will latch the Pass-Thru
address on the rising edge of this clock. This cycle is
also required to avoid contention on the DQ bus. Time
must be allowed after PTADR# is deasserted for the
DQ outputs to float before Add-On logic attempts to
write to the Pass-Thru Read FIFO.
Clock 9: As the S5320 samples WR# and PTRDY#
deasserted, no data was written to the PT Read FIFO
and the FIFO pointer was not updated (as the transfer
was not signaled complete via a PTRDY#). The Add-
On logic samples PTBURST# deasserted and
PTATN# asserted, so it knows that the previous data
transfer was the last, and no more data is being
requested. However, as it inserted a wait state during
the previous cycle, it still has one more transfer to
complete. As the Add-On logic is ready to complete
the transfer, it asserts WR# and drives the DQ bus
with DATA4. PTRDY# is also asserted to complete the
last data phase.
Clock 4: The BE[3:0]#, ADR[6:2], and SELECT#
inputs are asserted. WR# and DQ are asserted, indi-
cating that DATA1 is to be written to the PT Read FIFO
on the next clock. PTRDY# is asserted, to indicate the
completion of the current data phase.
Clock 5: As the S5320 samples WR# asserted, it
writes DATA1 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the first data transfer
and updates the internal FIFO pointers. The PTBE#
outputs are updated to indicate which bytes are valid
for the second transfer. The Add-On logic samples
PTBURST# asserted, so it knows more data is being
requested WR# remains asserted, and DATA2 is
driven onto DQ. PTRDY# is also asserted to complete
the current data phase.
Clock 10: As the S5320 samples WR# asserted, it
writes DATA4 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the last data transfer
and updates the internal FIFO pointers. The S5320
deasserts PTATN#, indicating that the final transfer
was performed. No more data is being requested from
PCI. Since the Add-On logic previously sampled
PTBURST# deasserted, and transferred the last data,
it knows that no more data is being requested. The
Add-On deasserts WR#, ADR[6:2], SELECT#,
BE[3:0]# and DQ. It also deasserts PTRDY#.
Clock 6: As the S5320 samples WR# asserted, it
writes DATA2 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the second data
transfer and updates the internal FIFO pointers. The
PTBE# outputs are updated to indicate which bytes
are valid for the third transfer. The Add-On logic sam-
ples PTBURST# asserted, so it knows more data is
being requested. However, it is not ready to transfer
data yet, so it deasserts PTRDY# and WR#, and stop
driving the DQ bus. The DQ bus could be in tri-state.
Clock 11: As PTATN# and PTBURST# are deas-
serted, the Pass-Thru access is complete, and the
S5320 can accept new Pass-Thru accesses starting
on the next clock. The other Pass-Thru signals can
also change state (in anticipation of a new transfer).
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface
in Passive Mode
Clock 7: As the S5320 samples WR# and PTRDY#
deasserted, no data was written to the PT Read FIFO
and the FIFO pointer was not updated (as the transfer
was not signaled complete via a PTRDY#). The Add-
On logic is ready to continue the transfer, so it asserts
WR# and drives the DQ bus with DATA3. PTRDY# is
also asserted to complete the current data phase.
The S5320 allows a simple interface to devices with 8-
bit or 16-bit data buses. Each Pass-Thru region may
be defined as 8, 16 or 32 bits, depending on the con-
tents of the boot device which is loaded into the PCI
Base Address Configuration Registers during initial-
ization. The result of the initialization is a unique
bussize (8/16/32 bits) for each Pass-Thru region. The
Pass-Thru Add-On interface internally controls byte
lane steering to allow access to the 32-bit Pass-Thru
Data FIFO (APTD) from 8-bit or 16-bit Add-On buses.
The four DQ data bytes are internally steered depend-
Clock 8: As the S5320 samples WR# asserted, it
writes DATA3 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the third data transfer
and updates the internal FIFO pointers. The S5320
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