TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
FUNCTIONAL BLOCKS OVERVIEW
FTI Interface
• Provides a high-speed interconnection between a
SONET/SDH physical layer device and a Link layer
device, or a SONET/SDH physical layer device and one
or more PDH physical layer devices.
• High bandwidth interface, capable of carrying an STS-12
bandwidth carrying 1xSTS-12c, 4xSTS-3c, 12xSTS-
1,12xDS3, 12xE3, 336xDS1/VT1.5/TU11 or 252xE1/
VT2/TU12 payloads, or any valid mix of the above.
• The Parallel version runs at a 77.76 MHz speed,
transferring 8-bits of data on every clock cycle and is
compatible with standard Telecom bus.
• The serial version transfers data bits in a 622.08 Mb/s
across a LVDS serial link.
• Supports byte floating (byte aligned) tributary bytes
aligned to system boundaries.
• Support both asynchronous (DS3/E3/DS1/E1) and
synchronous(VT1.5/VT2/TU11/TU12) payloads time
division multiplexed into the system frame.
• Support synchronous SONET mappings (STS-1/STS-3c/
STS-12c/VT1.5/VT2 synchronous payload envelopes).
FINAL
Product Brief
Part Number S4811, Rev. 2.4 July 2006
receive and the transmit direction.
• Optional pre format (X
43
+1) frame scrambling and post
de-format scrambling support on channels 0 to 47.
• Octet Alignment checking.
• Min/Max frame length checking.
• Abort sequence checking.
• 56Kb/s support with Idle bit control.
• Inter-frame fill control.
• Data Inversion control.
• Force bad CRC for diagnostics.
• Optional pass/discard errored frames per RX channel.
• Extensive Per channel statistics that include:
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Good Frame/Byte counts on both TX and RX.
FCS/CRC error counts on RX.
Octet alignment error counts on RX.
Frame length violations on RX.
Received frame aborts counts.
RX overrun events count.
TX aborts sent count.
ATM Processor
• 2047 user assignable channels.
• Supports direct ATM cell mappings for STS12c, STS3c,
STS1c, DS3, DS1, E1, DS0, and NxDS0.
• Supports G.832 ATM cell mapping for E3.
• Supports PLCP ATM cell mapping for DS3.
• Generates TX HEC and allows pass through of HEC
when configured for 56B cell mode on SPI-3.
• Optional TX Idle cell insertion.
• Configurable Idle cell format for inserted TX Idle cells.
• Performs RX cell delineation.
• Optional RX HEC checking.
• Optional RX HEC single bit correction.
• Optional payload scrambling using X
43
+1 polynomial.
• Optional RX Idle and/or Unassigned cell removal.
• Configurable Unassigned cell format for RX removal.
• Optional pass/discard error cells per channel in RX.
SPI-3 Interface
• Industry standard variable length packet interface
supporting transmit and receive data transfers at rates
independent of the line bit rate.
• Defines both byte-level and packet-level transfer control
in the transmit and receive direction.
• Support SPI-3 direct mode transfers.
• Support 52 byte and 56 byte cell formats transferred as
packets.
• 25MHz to 104MHz operation supported
HDLC Processor
• 2047 user assignable channels.
• HDLC frame structure is configurable to support POS/
PPP, HDLC, and direct map modes of operation.
• Bit/Byte synchronization and byte alignment together
with bit/byte stuffing and destuffing.
• RFC1662 standards compliant framing.
• Optional insertion and removal of PPP address and
control bytes.
• Optional generation and deletion of 16/32 bit frame
check sequence field (FCS).
• Payload transparency processing support in both the
Empowering Intelligent Optical Networks
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
