Revision 3.8 - May 2000
S1202 STS-12 ATM/DS3 SONET MAPPER
SUMMARY DATASHEET
The DS3 mapper accepts data from an external DS3 input,
from looped-back DS3 tributaries, or from internal DS3 frame
generators. The internal DS3 frame generators are used for
ATM, PLCP, or PRBS data. The S1202 maps the data into
STS-1 SONET payloads.
Overview and Applications
SONET Processing
The S1202 implements SONET/SDH processing and ATM
mapping functions for STS-12/STM-4 data streams. It can
support any combination of STS-12c, STS-3c, or STS-1 sig-
nals within an STS-12, or any combination of AU-4-4c or
AU-4 signals within an STM-4. In addition, it can support DS3
tributaries, in SONET, with provisionable support for clear
channel passthrough, direct mapping of ATM cells, or ATM
PLCP mapping. A TOH/SOH interface provides direct
add/drop capability for E1, E2, F1, and both Section and Line
DCC channels.
The S1202 DS3 de-mapper support includes the ability to
extracts DS3 or ATM data from the SONET signal. DS3 sig-
nals can contain ATM, PLCP, or clear channel DS3 data. For
ATM or PLCP data, the S1202 frames on the DS3 and
extracts these signals from the DS3 payload. For clear chan-
nel DS3 data, the S1202 generates RX serial (NRZ) data sig-
nals smoothed to match a DS3 clock input that is provided to
the device, as well as a FIFO Fill Indication, provided for
phase lock loop adjustment. The S1202 also provides full
DS3 framing, monitoring, and extraction for full DS3 support.
On the transmit side the S1202 generates section, line, &
path overhead. It performs framing pattern insertion (A1, A2),
scrambling, alarm signal insertion, and generates section,
line and path Bit Interleaved Parity (B1/B2/B3) for far-end
performance monitoring.
Line-side Interface
On the line-side, the S1202 supports an 8-bit parallel inter-
face which operates at 77.76 MHz. The device is typically
connected to a parallel-to-serial converter, which is in turn
connected to an electrical-to-optical converter for interfacing
to the fiber optic interface. (See figure below.)
On the receive side the S1202 processes section, line, & path
overhead. It performs payload framing (A1, A2), descram-
bling, alarm detection, Bit Interleaved Parity monitoring
(B1/B2/B3), and error count accumulation for performance
monitoring.
System Interface
The S1202 supports a UTOPIA Level 2 interface, operating at
50 Mb/s, for providing ATM cell transfers to/from the system
interface. The S1202 also supports up to 12 DS3 tributaries.
For clear channel DS3 data, the S1202 generates RX serial
(NRZ) data signals smoothed to match a DS3 clock input that
is provided to the device, as well as a FIFO Fill Indication,
provided for phase lock loop adjustment.
ATM Processing
When configured for ATM cell processing, the S1202 transmit
ATM processor will perform all necessary cell encapsulation
including HEC generation, cell level scrambling (X43+1), and
idle cell insertion to adapt the cell rate to the SPE. When
receiving data from the line side, it performs cell delineation,
Rx header control, descrambling, and receive cell rate adap-
tation.
DS3 Processing
The S1202 provides DS3 mapper and de-mapper functions.
Microprocessor
Control
TYPICAL APPLICATIONS
Reference
Clock
12
Data
8
Control
Channelized 622 Mb/s ATM Application
Addr
TX_CLK78
TX_CLK
TX_SYS_DAT[15:0]
U
T
O
P
I
SerTxD
SerRxD
Utopia Level-2
System Interface
TX_DATA[7:0]
P/S & S/P
SONET
Line Side
Interface
Fiber Optic
Transceiver
SONET XCVR
with
Clk Recovery
RX_CLK
RX_LOS
RX_CLK78
RX_SYS_DAT[15:0]
ATM Switch
A
RX_DATA[7:0]
AMCC
S1202
OR
HP HFCT5208
IP ROUTER
Switching/
AMCC S3032
TX_DS3_[1:12]_DATA
TX_DS3_[1:12]_CLK
RX_DS3_[1:12]_DATA
Sumitomo SDM7202
Multi
Channel
HDLC
DS3
Routing
Logic
Processor
RX_DS3_[1:12]_GAP/SM_CLK
RX_DS3_[1:12]_FIFO_[1:0]
TOH Insertion
and Extraction
DS3 Clear Channel for
Packet over SONET Application
AMCC
200 Brickstone Square, Andover, MA 01810 Ph: 978/623-0009 Fax:978/623-0024
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
