Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Signal Description
The PPC440SP embedded controller is packaged in a 783-ball flip-chip plastic ball grid array (FC-PBGA). The
following table describes the package level pinout.
Table 5. Pin Summary
Group
Signal pins, non-multiplexed
Signal pins, multiplexed
Total Signal Pins
AxVDD
No. of Pins
496
32
528
2
APxVDD
3
AxGND
5
OVDD (3.3V I/Os)
15
31
10
PxVDD (3.3V-1.5V PCI)
SVDD G(2.5-1.8V SDRAM)
VDD (1.5V Logic)
47
92
GND
Total Power Pins
Reserved
205
50
Total Pins
783
In the table “Signal Functional Description” on page 56, each I/O signal is listed along with a short description of its
function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed
Alphabetically” on page 17 for the pin (ball) number to which each signal is assigned.
54
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
