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440GX 参数 Datasheet PDF下载

440GX图片预览
型号: 440GX
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GX嵌入式处理器 [Power PC 440GX Embedded Processor]
分类和应用: PC
文件页数/大小: 93 页 / 1501 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.15 – August 30, 2007  
440GX – Power PC 440GX Embedded Processor  
Data Sheet  
Signal Functional Description (Sheet 2 of 8)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
PCIXTRDY  
Description  
I/O  
Type  
Notes  
Indicates the target agent’s ability to complete the current data  
phase of the transaction.  
I/O  
3.3V PCI  
4
DDR SDRAM Interface  
BA0:1  
Bank Address supporting up to four internal banks.  
Selects up to four external DDR SDRAM banks.  
Column Address Strobe.  
O
O
O
O
2.5V SSTL_2  
2.5V SSTL_2  
2.5V SSTL_2  
2.5V SSTL_2  
BankSel0:3  
CAS  
ClkEn0:3  
Clock Enable. One for each bank.  
Memory write data byte lane masks. MEMDM8 is the byte lane  
mask for the ECC byte lane.  
DM0:8  
O
2.5V SSTL_2  
2.5V SSTL_2  
Byte lane data strobe. DQS8 is the data strobe for the ECC byte  
lane.  
DQS0:8  
I/O  
ECC0:7  
ECC check bits 0:7.  
Memory address bus.  
I/O  
O
2.5V SSTL_2  
2.5V SSTL_2  
MemAddr00:12  
MemClkOut0  
MemClkOut0  
Subsystem clock.  
O
I/O  
I
2.5V SSTL_2  
2.5V SSTL_2  
MemData00:63  
MemVRef1:2  
Memory data bus.  
Voltage Ref  
Receiver  
Memory reference voltage (SVREF) input.  
RAS  
Row Address Strobe.  
Write Enable.  
O
O
2.5V SSTL_2  
2.5V SSTL_2  
WE  
Ethernet Interface  
EMCCD,  
MII: Collision detection  
RMII 1: Receive error  
GMII: 1000Mbps Transmit clock  
RGMII: Transmit clock  
TBI: Transmit clock  
EMC1RxErr,  
GMCGTxClk,  
GMC0TxClk,  
TBITxClk,  
3.3V tolerant  
2.5V CMOS  
I/O  
I/O  
RTBI0TxClk  
RTBI: Transmit clock  
EMCCrS,  
MII: Carrier sense  
EMC0CrSDV,  
GMCTxD7,  
GMC1TxD3,  
TBITxD7,  
RMII 0: Carrier sense data valid  
GMII: Transmit data  
RGMII 1: Transmit data  
TBI: Transmit data  
3.3V tolerant  
2.5V CMOS  
RTBI1TxD3  
RTBI 1: Transmit data  
3.3V tolerant  
2.5V CMOS  
EMCMDClk  
EMCMDIO  
MII and RMII: Management data clock  
O
MII and RMII: Transfer command and status information between  
MII and PHY  
3.3V tolerant  
2.5V CMOS  
I/O  
AMCC  
51  
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