Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Table 9. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
NAND Flash Interface
NFALE
Description
I/O
Type
Notes
Address Latch Enable.
O
O
3.3V LVTTL
3.3V LVTTL
1
1
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
Command Latch Enable.
NFCLE
O
3.3V LVTTL
1
Latches operational commands into the NAND Flash.
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-OR connected from all NAND Flash
devices.
NFRdyBusy
I
3.3V LVTTL
1
Read Enable.
NFREn
NFWEn
O
O
3.3V LVTTL
3.3V LVTTL
1
1
Data is latched on the rising edge.
Write Enable.
Data is latched on the rising edge.
Serial Peripheral Interface
SCPClkOut
Clock output.
Data input.
I/O
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
SCPDI
SCPDO
Data output.
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
External interrupt request 5.
I/O
I
3.3V LVTTL
1
1, 5
1
3.3V LVTTL
Rcvr
IRQ5
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
JTAG Interface
3.3V LVTTL
w/pull-up
TCK
Test Clock.
I
1
3.3V LVTTL
w/pull-up
TDI
Test Data In.
I
O
I
1, 4
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
3.3V LVTTL
w/pull-up
TRST
Test Reset.
I
1, 5
AMCC Proprietary
61
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
