Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Ethernet Controller
Preliminary Data Sheet
Ethernet support provided by the PPC440GRx interfaces to the physical layer but the PHY is not included on the
chip:
• Two 10/100/1000 interfaces running in full- and half-duplex modes providing:
– One Gigabit Media Independent Interface (GMII)
– One Media Independent Interface (MII)
– Two Reduced Gigabit MII (RGMII)
– Two Serial MII (SMII) at 100/10Mbps.
– Packet reject support
– Jumbo frame support
– DMA capability
– Interrupt coalescence
DMA-to-PLB3 (64-bit) Controller
This DMA controller provides a DMA interface between OPB0 and PLB3.
Features include:
• Supports the following transfers:
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 32-byte buffer
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
Serial Ports (UART)
Features include:
• Up to four ports in the following combinations:
– One 8-pin (UART0)
– Two 4-pin (UART0 and UART1)
– One 4-pin (UART0) and two 2-pin (UART1 and UART2)
– Four 2-pin (UART0, UART1, UART2, and UART3)
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with NS16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA function on PLB3
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AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
