Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Table 21. I/O Specifications—400MHz to 667MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr02:31
PerBLast
n/a
4
n/a
1
6
n/a
6
1
n/a
1
19.1
n/a
8.7
n/a
8.7
8.7
8.7
8.7
8.7
6.6
8.7
8.7
8.7
8.7
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
4
1
19.1
19.1
19.1
19.1
19.1
14.6
19.1
19.1
19.1
19.1
4
1
6
1
4
1
6
1
PerCS0:5
n/a
4
n/a
1
6
1
PerData00:15
PerData16:31
PerOE
6
1
4
1
6
1
n/a
4
n/a
1
6
1
PerReady
n/a
6
n/a
1
PerR/W
4
1
PerWBE0:1
4
1
6
1
External Master Peripheral Interface
BusReq
n/a
n/a
4
n/a
n/a
1
6
6
1
1
19.1
19.1
19.1
19.1
19.1
n/a
8.7
8.7
8.7
8.7
8.7
n/a
n/a
8.7
n/a
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
ExtAck
ExtReq
n/a
6
n/a
1
ExtReset
HoldAck
HoldReq
HoldPri
n/a
n/a
4
n/a
n/a
1
6
1
n/a
n/a
n/a
n/a
4
1
n/a
PerClk
19.1
n/a
PLB Clk
PerClk
1
PerErr
4
1
n/a
n/a
NAND Flash Interface
NFALE
n/a
n/a
n/a
4
n/a
n/a
n/a
1
6
6
1
1
19.1
19.1
19.1
n/a
8.7
8.7
8.7
n/a
8.7
8.7
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
NFCE0:3
NFCLE
6
1
NFRdyBusy
NFREn
n/a
6
n/a
1
n/a
n/a
n/a
n/a
19.1
19.1
NFWEn
6
1
84
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