Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
more details)
• Direct 8-bit interfacing to discrete NAND Flash devices
• Up to four banks of NAND Flash supported
• Device size 4MB-256MB (32Mb to 2Gb) supported
• 512B + 16B or 2kB + 64B device page sizes supported
• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED)
• Eight-bit command write, address write, and data read/write
• Interrupt on device ready (after long page write or block erase operations)
• Boot from NAND
– Executes up to 4 KB of boot code out of first block
– Automatic page read accesses performed based on device configuration and read address
DMA Controller
The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data
transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller
handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an
independent set of registers needed for data transfer: a control register, a source address register, a destination
address register, and a transfer count register.
Features include:
• Memory-to-memory transfers
• Buffered memory-to-peripheral transfers
• Buffered peripheral-to-memory transfers
• Four independent DMA channels
• Scatter/gather capability for dynamically programming multiple DMA transfers
• Programmable address increment or decrement
• Internal data buffering
• Can transfer data to/from any PLB and OPB slave, including OCM and external bus
USB Interface
The USB support provides separate Host and Device interfaces compliant with the USB1.1 Specification
Features include:
• USB1.1 Host (2 ports)
– Compliant with USB 1.1 Specification and OHCI version 1.0a Host Controller Specification
– Compatible with USB 2.0 Full-Speed peripherals
– Supports Low-Speed (1.5Mbps) operation
– All transfer types (Isochronous, Interrupt, Control, and Bulk) supported
– Tx and Rx FIFOs: 16-entries x 32-bits each
– Independent 32-bit OPB master and slave interfaces (master and slave can operate asynchronously)
– Programmable OPB slave base address
– Up to 127 connected devices supported
• USB1.1 Device (1 port)
– Full- and Low-Speed device controller
– 32-bit, OPB slave interface
– Three Endpoints supported (Endpoint 0 is used for control)
• Endpoints 1–2 can be IN, OUT, IN and OUT, IN/OUT programmable
• Endpoints 1–2 configurable to support Interrupt/Bulk only, Isochronous only, Interrupt/Bulk or
Isochronous (programmable) transfer types
• Endpoints 1–2 configurable to support maximum packet size of 8, 16, 32, or 64 bytes
• Endpoint 0 configurable to support maximum packet size of 8 or 16 bytes
• Full Speed (12 Mbps) USB PHY for each of the 3 USB ports
– Tolerates shorting to 5.25V and shorting to ground if driving signal conditions meet those specified in the
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AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
