MAX 9000 Programmable Logic Device Family Data Sheet
Table 23. IOC Delays
Symbol
Parameter
Conditions
Speed Grade
-15
Unit
-10
-20
Min Max Min Max Min Max
tIODR
tIODC
I/O row output data delay
I/O column output data delay
I/O control delay
0.2
0.4
0.2
0.2
1.5
1.5
ns
ns
tIOC
(6)
0.5
0.6
1.0
1.0
2.0
1.5
ns
ns
tIORD
I/O register clock-to-output
delay
tIOCOMB
tIOSU
I/O combinatorial delay
0.2
1.0
1.5
ns
ns
I/O register setup time before
clock
2.0
1.0
4.0
1.0
5.0
1.0
tIOH
I/O register hold time after
clock
ns
tIOCLR
tIOFD
I/O register clear delay
1.5
0.0
3.5
3.0
0.0
4.5
3.0
0.5
5.5
ns
ns
ns
I/O register feedback delay
tINREG
I/O input pad and buffer to I/O
register delay
tINCOMB
tOD1
I/O input pad and buffer to row
and column delay
1.5
1.8
2.0
2.5
2.5
2.5
ns
ns
Output buffer and pad delay, C1 = 35 pF
Slow slew rate = off,
VCCIO = 5.0 V
tOD2
Output buffer and pad delay, C1 = 35 pF
Slow slew rate = off,
2.3
8.3
3.5
3.5
ns
ns
V
CCIO = 3.3 V
tOD3
Output buffer and pad delay, C1 = 35 pF
Slow slew rate = on,
10.0
10.5
V
CCIO = 5.0 V or 3.3 V
tXZ
Output buffer disable delay
C1 = 5 pF
2.5
2.5
2.5
2.5
2.5
2.5
ns
ns
tZX1
Output buffer enable delay,
Slow slew rate = off,
VCCIO = 5.0 V
C1 = 35 pF
tZX2
Output buffer enable delay,
Slow slew rate = off,
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
3.0
9.0
3.5
3.5
ns
ns
tZX3
Output buffer enable delay,
Slow slew rate = on,
10.0
10.5
VCCIO = 3.3 V or 5.0 V
34
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
