MAX 9000 Programmable Logic Device Family Data Sheet
Table 22. MAX 9000 Internal Timing Characteristics
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-15
Unit
-10
-20
Min Max Min Max Min Max
tLAD
tLAC
tI C
Logic array delay
3.5
3.5
3.5
3.5
3.5
0.5
0.5
0.4
4.0
4.0
4.0
4.0
5.0
1.0
1.0
1.0
4.5
4.5
4.5
4.5
7.5
2.0
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Logic control array delay
Array clock delay
tEN
Register enable time
Shared expander delay
Parallel expander delay
Register delay
tSEXP
tPEXP
tRD
tCOMB
tSU
Combinatorial delay
Register setup time
Register hold time
Register preset time
Register clear time
FastTrack drive delay
Low-power adder
2.4
2.0
3.0
3.5
4.0
4.5
tH
tPRE
tCLR
tFTD
tLPA
3.5
3.7
4.0
4.0
4.5
4.5
0.5
1.0
2.0
(5)
10.0
15.0
20.0
Altera Corporation
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