MAX 9000 Programmable Logic Device Family Data Sheet
Tables 21 through 24 show timing for MAX 9000 devices.
Table 21. MAX 9000 External Timing Characteristics
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-15
Unit
-10
-20
Min Max Min Max Min Max
tPD1
tPD2
Row I/O pin input to row I/O
pin output
C1 = 35 pF (2)
10.0
15.0
20.0
ns
Column I/O pin input to
column I/O pin output
C1 = 35 pF EPM9320A
10.8
ns
ns
ns
ns
ns
ns
ns
(2)
EPM9320
16.0
16.2
16.4
23.0
23.2
23.4
EPM9400
EPM9480
EPM9560A
EPM9560
11.4
16.6
23.6
tFSU
tFH
Global clock setup time for I/O
cell
3.0
0.0
5.0
0.0
6.0
0.0
Global clock hold time for I/O
cell
ns
ns
tFCO
tCNT
fCNT
Global clock to I/O cell output C1 = 35 pF
delay
1.0 (3)
4.8
6.9
1.0 (3)
7.0
8.5
1.0 (3)
8.5
Minimum internal global clock (4)
period
10.0
ns
Maximum internal global clock (4)
144.9
117.6
100.0
MHz
frequency
32
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
