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EPM9560A 参数 Datasheet PDF下载

EPM9560A图片预览
型号: EPM9560A
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件
文件页数/大小: 46 页 / 495 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 9000 Programmable Logic Device Family Data Sheet  
The MAX 9000 family of in-system-programmable, high-density, high-  
performance EPLDs is based on Alteras third-generation MAX  
architecture. Fabricated on an advanced CMOS technology, the EEPROM-  
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin  
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed  
grade of the MAX 9000 family is compliant with the PCI Local Bus  
Specification, Revision 2.2. Table 3 shows the speed grades available for  
MAX 9000 devices.  
General  
Description  
Table 3. MAX 9000 Speed Grade Availability  
Device  
Speed Grade  
-10  
-15  
-20  
EPM9320  
EPM9320A  
EPM9400  
EPM9480  
EPM9560  
EPM9560A  
v
v
v
v
v
v
v
v
v
v
Table 4 shows the performance of MAX 9000 devices for typical functions.  
Table 4. MAX 9000 Performance  
Note (1)  
Application  
Macrocells Used  
Speed Grade  
-15  
Units  
-10  
-20  
16-bit loadable counter  
16-bit up/down counter  
16-bit prescaled counter  
16-bit address decode  
16-to-1 multiplexer  
16  
16  
16  
1
144  
144  
118  
118  
100  
100  
MHz  
MHz  
MHz  
ns  
144  
118  
100  
5.6 (10)  
7.7 (12.1)  
7.9 (15)  
10.9 (18)  
10 (20)  
16 (26)  
1
ns  
Note:  
(1) Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row  
input pin to row I/ O pin.  
The MAX 9000 architecture supports high-density integration of system-  
level logic functions. It easily integrates multiple programmable logic  
devices ranging from PALs, GALs, and 22V10s to field-programmable  
gate array (FPGA) devices and EPLDs.  
Altera Corporation  
3