MAX 7000A Programmable Logic Device Data Sheet
The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See Table 3 and Table 4.
Table 3. MAX 7000A Maximum User I/O Pins
Note (1)
Device
44-Pin PLCC 44-Pin TQFP 49-Pin Ultra 84-Pin PLCC
100-Pin
TQFP
100-Pin
FineLine
BGA (3)
FineLine
BGA (2)
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
36
36
36
36
41
68
84
84
84
84
68
84
84
68
68
84
Table 4. MAX 7000A Maximum User I/O Pins
Note (1)
Device
144-Pin TQFP
169-Pin Ultra
FineLine BGA (2)
208-Pin PQFP 256-Pin BGA 256-Pin FineLine
BGA (3)
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
100
100
120
120
120
100
100
100
164
164
176
164
164
212
212
Notes to tables:
(1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(2) All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more
details.
(3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details.
4
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